[USRP-users] Digital Down-conversion by FPGA

[Activecat]

ah ok, sorry, yes, that makes sense; might have had my head elsewhere
yesterday.
Greetings,
Marcus

Hello,

that depends on your device. For N210 it's 250kS/s, since that's the
fixed Master Clock Rate 100MHz divided by the maximum decimation rate.

as far as I know, the maximum decimation rate is 512, so the minimum
sampling frequency is ~195.3 kHz (I routinely use 200 kHz sampling rate)
Cheers,
Daniele

I have a BasicRX plugged into N210 to perform bandpass sampling.
In GRC flowgraph the UHD source is configured as: sample rate = 200kHz,
Center Freq=0
In this case I want to sample the incoming signal at barely 200kHz.

I understand that the N210 ADC always runs at 100MHz sample rate.
I just want to confirm that, in this case, there will be no digital
down-conversion (DDC) done by the FPGA of N210.
If this is true, then out of every 500 samples obtained by the ADC, only
one of them is sent to the host/PC, the other 499 samples are scrapped.

Could someone confirm on this ?
Thanks a lot.

Note: 100MHz / 200kHz = 500

[Marcus D. Leech]

Post by Activecat
I have a BasicRX plugged into N210 to perform bandpass sampling.
In GRC flowgraph the UHD source is configured as: sample rate =
200kHz, Center Freq=0
In this case I want to sample the incoming signal at barely 200kHz.
I understand that the N210 ADC always runs at 100MHz sample rate.
I just want to confirm that, in this case, there will be no digital
down-conversion (DDC) done by the FPGA of N210.
If this is true, then out of every 500 samples obtained by the ADC,
only one of them is sent to the host/PC, the other 499 samples are
scrapped.
Could someone confirm on this ?
Thanks a lot.
Note: 100MHz / 200kHz = 500

As far as I know, it still goes through the CIC decimator, it doesn't
just discard samples, but properly downsamples them, even though it's doing
no frequency adjustment.

[Activecat]

On Tue, Aug 12, 2014 at 9:27 AM, Marcus D. Leech via USRP-users <

Post by Marcus D. Leech

Post by Activecat
I have a BasicRX plugged into N210 to perform bandpass sampling.
In GRC flowgraph the UHD source is configured as: sample rate = 200kHz,
Center Freq=0
In this case I want to sample the incoming signal at barely 200kHz.
I understand that the N210 ADC always runs at 100MHz sample rate.
I just want to confirm that, in this case, there will be no digital
down-conversion (DDC) done by the FPGA of N210.
If this is true, then out of every 500 samples obtained by the ADC, only
one of them is sent to the host/PC, the other 499 samples are scrapped.
Could someone confirm on this ?
Thanks a lot.
Note: 100MHz / 200kHz = 500
As far as I know, it still goes through the CIC decimator, it doesn't

just discard samples, but properly downsamples them, even though it's doing
no frequency adjustment.

Downsample must happen with a known downsampling frequency.
When we configure "Center Freq=0", how much is the downsampling frequecy
being used?

Probably the best way is to look at the FPGA code, unfortunately I am not
able to do so.
Could anyone help me on this ..?

[Ian Buckley]

No in-coming samples are discarded. The signal will be decimated in three discrete stages; by 125 in a CIC filter, then by 2 in a half band FIR and then again by 2 in a second half band FIR.
Clearly no downconversion will occur since the center frequency has been set to 0Hz.

Post by Activecat
I have a BasicRX plugged into N210 to perform bandpass sampling.
In GRC flowgraph the UHD source is configured as: sample rate = 200kHz, Center Freq=0
In this case I want to sample the incoming signal at barely 200kHz.
I understand that the N210 ADC always runs at 100MHz sample rate.
I just want to confirm that, in this case, there will be no digital down-conversion (DDC) done by the FPGA of N210.
If this is true, then out of every 500 samples obtained by the ADC, only one of them is sent to the host/PC, the other 499 samples are scrapped.
Could someone confirm on this ?
Thanks a lot.
Note: 100MHz / 200kHz = 500
As far as I know, it still goes through the CIC decimator, it doesn't just discard samples, but properly downsamples them, even though it's doing
no frequency adjustment.
Downsample must happen with a known downsampling frequency.
When we configure "Center Freq=0", how much is the downsampling frequecy being used?
Probably the best way is to look at the FPGA code, unfortunately I am not able to do so.
Could anyone help me on this ..?
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[Activecat]

Thanks, this answer is sufficient.

Another scenario:
Now the N210 is configured as: Sample Rate = 100MHz, Center Freq = 0.
In fact I wish to get the samples directly from the ADC, since it is
running at 100MHz.
But again the samples need to go through the CIC first, before going to the
host (PC).

Question:
How to make the CIC passes the samples to the host (PC) without
significantly modifying the samples ?

Note:
If the samples can transparently 'pass through' the CIC, then I could
actually create a gnuradio custom block to discard 499 samples out of every
500 samples, to achieve what I want earlier.

Post by Ian Buckley
No in-coming samples are discarded. The signal will be decimated in three
discrete stages; by 125 in a CIC filter, then by 2 in a half band FIR and
then again by 2 in a second half band FIR.
Clearly no downconversion will occur since the center frequency has been set to 0Hz.
On Aug 11, 2014, at 7:57 PM, Activecat via USRP-users <
On Tue, Aug 12, 2014 at 9:27 AM, Marcus D. Leech via USRP-users <

Post by Marcus D. Leech

Post by Activecat
I have a BasicRX plugged into N210 to perform bandpass sampling.
In GRC flowgraph the UHD source is configured as: sample rate = 200kHz, Center Freq=0
In this case I want to sample the incoming signal at barely 200kHz.
I understand that the N210 ADC always runs at 100MHz sample rate.
I just want to confirm that, in this case, there will be no digital
down-conversion (DDC) done by the FPGA of N210.
If this is true, then out of every 500 samples obtained by the ADC, only
one of them is sent to the host/PC, the other 499 samples are scrapped.
Could someone confirm on this ?
Thanks a lot.
Note: 100MHz / 200kHz = 500
As far as I know, it still goes through the CIC decimator, it doesn't

just discard samples, but properly downsamples them, even though it's doing
no frequency adjustment.

Downsample must happen with a known downsampling frequency.
When we configure "Center Freq=0", how much is the downsampling frequecy being used?
Probably the best way is to look at the FPGA code, unfortunately I am not able to do so.
Could anyone help me on this ..?
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[Marcus D. Leech]

Post by Activecat
Thanks, this answer is sufficient.
Now the N210 is configured as: Sample Rate = 100MHz, Center Freq = 0.
In fact I wish to get the samples directly from the ADC, since it is
running at 100MHz.
But again the samples need to go through the CIC first, before going
to the host (PC).
How to make the CIC passes the samples to the host (PC) without
significantly modifying the samples ?
If the samples can transparently 'pass through' the CIC, then I could
actually create a gnuradio custom block to discard 499 samples out of
every 500 samples, to achieve what I want earlier.

There's no way to carry 100Msps complex across 1GiGe, unless you carry
4-bit samples across the wire, and there's no way to do that without
modifying
the FPGA code.

Post by Activecat
No in-coming samples are discarded. The signal will be decimated
in three discrete stages; by 125 in a CIC filter, then by 2 in a
half band FIR and then again by 2 in a second half band FIR.
Clearly no downconversion will occur since the center frequency
has been set to 0Hz.
On Aug 11, 2014, at 7:57 PM, Activecat via USRP-users

Post by Activecat
On Tue, Aug 12, 2014 at 9:27 AM, Marcus D. Leech via USRP-users
I have a BasicRX plugged into N210 to perform bandpass sampling.
In GRC flowgraph the UHD source is configured as: sample
rate = 200kHz, Center Freq=0
In this case I want to sample the incoming signal at
barely 200kHz.
I understand that the N210 ADC always runs at 100MHz sample rate.
I just want to confirm that, in this case, there will be
no digital down-conversion (DDC) done by the FPGA of N210.
If this is true, then out of every 500 samples obtained
by the ADC, only one of them is sent to the host/PC, the
other 499 samples are scrapped.
Could someone confirm on this ?
Thanks a lot.
Note: 100MHz / 200kHz = 500
As far as I know, it still goes through the CIC decimator, it
doesn't just discard samples, but properly downsamples them,
even though it's doing
no frequency adjustment.
Downsample must happen with a known downsampling frequency.
When we configure "Center Freq=0", how much is the downsampling
frequecy being used?
Probably the best way is to look at the FPGA code, unfortunately
I am not able to do so.
Could anyone help me on this ..?
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[Activecat]

Post by Activecat
Thanks, this answer is sufficient.
Now the N210 is configured as: Sample Rate = 100MHz, Center Freq = 0.
In fact I wish to get the samples directly from the ADC, since it is
running at 100MHz.
But again the samples need to go through the CIC first, before going to
the host (PC).
How to make the CIC passes the samples to the host (PC) without
significantly modifying the samples ?
If the samples can transparently 'pass through' the CIC, then I could
actually create a gnuradio custom block to discard 499 samples out of every
500 samples, to achieve what I want earlier.
There's no way to carry 100Msps complex across 1GiGe, unless you
carry 4-bit samples across the wire, and there's no way to do that without
modifying
the FPGA code.

Thank you, Marcus.

In fact I am trying to perform bandpass sampling.
I need the host (PC) to get the raw sample at 200kS/s, ideally the samples
should not be "pre-processed" by CIC or any other FPGA logic.
As the 100MS/s of the ADC cannot be changed, it seems that I have no other
choice but to reprogram the FPGA..

[Marcus Müller]

Hi Activecat,

I still don't understand why you don't want the decimation filters --
you *need* them, unless you want to have massive aliasing of signals

Post by Activecat

200kHz into your bandpass signal. Decimation without filtering is a

big signal theoretical no-go.

I think I effectively need you to explain in something like a frequency
chart, which information you want to get out of the USRP.

Greetings,
Marcus

Post by Activecat

Thanks, this answer is sufficient.
Now the N210 is configured as: Sample Rate = 100MHz, Center Freq = 0.
In fact I wish to get the samples directly from the ADC, since it is
running at 100MHz.
But again the samples need to go through the CIC first, before going to
the host (PC).
How to make the CIC passes the samples to the host (PC) without
significantly modifying the samples ?
If the samples can transparently 'pass through' the CIC, then I could
actually create a gnuradio custom block to discard 499 samples out of every
500 samples, to achieve what I want earlier.
There's no way to carry 100Msps complex across 1GiGe, unless you
carry 4-bit samples across the wire, and there's no way to do that without
modifying
the FPGA code.

Thank you, Marcus.
In fact I am trying to perform bandpass sampling.
I need the host (PC) to get the raw sample at 200kS/s, ideally the samples
should not be "pre-processed" by CIC or any other FPGA logic.
As the 100MS/s of the ADC cannot be changed, it seems that I have no other
choice but to reprogram the FPGA..
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[Activecat]

Post by Marcus Müller
Hi Activecat,
I still don't understand why you don't want the decimation filters -- you
*need* them, unless you want to have massive aliasing of signals >>200kHz
into your bandpass signal. Decimation without filtering is a big signal
theoretical no-go.
I think I effectively need you to explain in something like a frequency
chart, which information you want to get out of the USRP.
Greetings,
Marcus

What I try to get out of the USRP, is the raw data that is shown in figure
2-8 of the attached file.

[Marcus D. Leech]

On Tue, Aug 12, 2014 at 8:54 PM, Marcus MÃŒller
Hi Activecat,
I still don't understand why you don't want the decimation filters
-- you *need* them, unless you want to have massive aliasing of
signals >>200kHz into your bandpass signal. Decimation without
filtering is a big signal theoretical no-go.
I think I effectively need you to explain in something like a
frequency chart, which information you want to get out of the USRP.
Greetings,
Marcus
What I try to get out of the USRP, is the raw data that is shown in
figure 2-8 of the attached file.
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

If this is just an intellectual exercise, you can just use a BASIC_RX
card, which has analog bandwidth up to 250MHz, and apply a 150Mhz signal
to it, tuning the N2xx to where the alias frequency should appear and
confirm that, yes, there really is a Nyquist sampling theorem.

If it's for some *practical* purpose, then making use of the facilities
that the N2xx DSP has to offer makes the most sense.

If you are concerned that somehow all that digital "stuff" in the N2xx
DSP chain will somehow muck with the "purity" of your signal, or the
"truth" of it, then you should understand that everything out *in
front* of the ADC is more likely to cause you non-repeatability grief than
*anything* in the DSP chain. Such is the way of the analog world,
and it becomes more noticeable as ADC resolutions increase....

[Activecat]

On Wed, Aug 13, 2014 at 9:18 AM, Marcus D. Leech via USRP-users <

On Tue, Aug 12, 2014 at 8:54 PM, Marcus MÃŒller <

Post by Marcus Müller
Hi Activecat,
I still don't understand why you don't want the decimation filters -- you
*need* them, unless you want to have massive aliasing of signals >>200kHz
into your bandpass signal. Decimation without filtering is a big signal
theoretical no-go.
I think I effectively need you to explain in something like a frequency
chart, which information you want to get out of the USRP.
Greetings,
Marcus

What I try to get out of the USRP, is the raw data that is shown in
figure 2-8 of the attached file.
If this is just an intellectual exercise, you can just use a BASIC_RX
card, which has analog bandwidth up to 250MHz, and apply a 150Mhz signal
to it, tuning the N2xx to where the alias frequency should appear and
confirm that, yes, there really is a Nyquist sampling theorem.

I have successfully applied 4.00001GHz signal to a BASIC_RX card, with
sample rate of 200kHz it gains a 10kHz intermediate frequency. This is a
successful attempt.

When I want to publish the result, others may question me whether the
sampling is really done at 200kHz, or in fact 100MHz.
I am stumble.

[Marcus Müller]

Of course it's done at 100MHz, and it is, by applying the well-known
principles of digital signal processing, properly decimated to 200kHz.
I don't think anyone with a signal processing background would doubt you
if you describe the sampling-shifting-filtering-decimation signal chain
in your publication.

I, for one, however doubt that you successfully saw a lot of your
4.00001e9Hz signal, because the basicRX has an analog cutoff frequency
roughly at 500MHz [1]. The transformer doesn't seem to work much further
than 800MHz [2]. How much signal power did you feed into the SMA port?

As Marcus Leech said: Analog is the part of the signal chain that's hard
to prove. Just consider this: When subsampling a 4GHz signal with a
100MHz ADC, there's 39 alias regions you'll have to suppress with your
4GHz-centered bandpass analog filter. Now, let's assume that adjustable
bandpass filter is cool, it has a reliable attenuation of 30dB outside
the desired band [4]; Sadly, there's about 96dBHz bandwidth below your
desired bandwidth alone, or about 16dB as much bandpasses that you'll
have to suppress below your desired frequency. That would imply that the
average power below your desired band only sees an attenuation of
16dB-30dB=14dB=25lin; and that's not even considering signals at
frequencies above your desired passband!

That's one reason why one usually doesn't do Software Radio with
undersampling alone, but with multiple stages of filtering [3] and
mixers that bring down the RF signal to complex baseband.

Greetings,
Marcus

[1] http://files.ettus.com/manual/page_dboards.html#dboards_basicrx
[2] I think the limiting part is the RLC formed by the ADT-1WT
transformer, http://217.34.103.131/pdfs/ADT1-1WT.pdf.
[3] Try to spot all the filters in the WBX design,
http://files.ettus.com/schematics/wbx/wbx.pdf
[4] just a random number I guessed. But it kind of fits the bill:
compare the 2-3.9GHz adjustable filter from
http://www.hittite.com/content/documents/newsletters/0510_tunable_filters.pdf

Post by Activecat
On Wed, Aug 13, 2014 at 9:18 AM, Marcus D. Leech via USRP-users <

On Tue, Aug 12, 2014 at 8:54 PM, Marcus Müller <

Post by Marcus Müller
Hi Activecat,
I still don't understand why you don't want the decimation filters -- you
*need* them, unless you want to have massive aliasing of signals >>200kHz
into your bandpass signal. Decimation without filtering is a big signal
theoretical no-go.
I think I effectively need you to explain in something like a frequency
chart, which information you want to get out of the USRP.
Greetings,
Marcus

What I try to get out of the USRP, is the raw data that is shown in
figure 2-8 of the attached file.
If this is just an intellectual exercise, you can just use a BASIC_RX
card, which has analog bandwidth up to 250MHz, and apply a 150Mhz signal
to it, tuning the N2xx to where the alias frequency should appear and
confirm that, yes, there really is a Nyquist sampling theorem.

I have successfully applied 4.00001GHz signal to a BASIC_RX card, with
sample rate of 200kHz it gains a 10kHz intermediate frequency. This is a
successful attempt.
When I want to publish the result, others may question me whether the
sampling is really done at 200kHz, or in fact 100MHz.
I am stumble.
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[Activecat]

Hi Marcus,

The transmitter is N210 with SBX.
The uhd sink takes in complex data which its real and imag values are
either 0.7, 0 or -0.7.
I guess the transmitter power is near to 100mW.
Below is uhd part of the transmitter flowgraph:

self.uhd_usrp_sink_0_0 = uhd.usrp_sink(
",".join(("addr=192.168.10.2", "")),
uhd.stream_args(
cpu_format="fc32",
otw_format="sc16",
channels=range(1),
),
)
self.uhd_usrp_sink_0_0.set_clock_source("internal", 0)
self.uhd_usrp_sink_0_0.set_samp_rate(samp_rate)
self.uhd_usrp_sink_0_0.set_center_freq(4000.01e6, 0)
self.uhd_usrp_sink_0_0.set_gain(0, 0)


The SBX transmit directly to BASIC_RX via a direct cable, without any
attenuator.
A 30dB attenuator is needed if the carrier frequency is 400MHz, but must be
removed at carrier frequency of 4GHz.

Below is uhd part of the receiver flowpgrah:

self.uhd_usrp_source_0 = uhd.usrp_source(
",".join(("addr=192.168.10.3", "")),
uhd.stream_args(
cpu_format="fc32",
otw_format="sc16",
channels=range(1),
),
)
self.uhd_usrp_source_0.set_clock_source("mimo", 0)
self.uhd_usrp_source_0.set_samp_rate(samp_rate)
self.uhd_usrp_source_0.set_center_freq(0, 0)
self.uhd_usrp_source_0.set_gain(0, 0)

The uhd source outputs will be multiplied by 1,300 to become 1.0 ~ 2.0 in
amplitude.
This show that 4GHz RF still pass through the transformer of BASIC_RX but
with high attenuation.
I am not sure whether
1). will this spoil the hardware in long run
2). does this result in high noise added by the transformer of BASIC_RX ?

Post by Marcus Müller
Of course it's done at 100MHz, and it is, by applying the well-known
principles of digital signal processing, properly decimated to 200kHz.
I don't think anyone with a signal processing background would doubt you
if you describe the sampling-shifting-filtering-decimation signal chain in
your publication.
I, for one, however doubt that you successfully saw a lot of your
4.00001e9Hz signal, because the basicRX has an analog cutoff frequency
roughly at 500MHz [1]. The transformer doesn't seem to work much further
than 800MHz [2]. How much signal power did you feed into the SMA port?
As Marcus Leech said: Analog is the part of the signal chain that's hard
to prove. Just consider this: When subsampling a 4GHz signal with a 100MHz
ADC, there's 39 alias regions you'll have to suppress with your
4GHz-centered bandpass analog filter. Now, let's assume that adjustable
bandpass filter is cool, it has a reliable attenuation of 30dB outside the
desired band [4]; Sadly, there's about 96dBHz bandwidth below your desired
bandwidth alone, or about 16dB as much bandpasses that you'll have to
suppress below your desired frequency. That would imply that the average
power below your desired band only sees an attenuation of
16dB-30dB=14dB=25lin; and that's not even considering signals at
frequencies above your desired passband!
That's one reason why one usually doesn't do Software Radio with
undersampling alone, but with multiple stages of filtering [3] and mixers
that bring down the RF signal to complex baseband.
Greetings,
Marcus
[1] http://files.ettus.com/manual/page_dboards.html#dboards_basicrx
[2] I think the limiting part is the RLC formed by the ADT-1WT
transformer, http://217.34.103.131/pdfs/ADT1-1WT.pdf.
[3] Try to spot all the filters in the WBX design,
http://files.ettus.com/schematics/wbx/wbx.pdf
[4] just a random number I guessed. But it kind of fits the bill: compare
the 2-3.9GHz adjustable filter from
http://www.hittite.com/content/documents/newsletters/0510_tunable_filters.pdf
Hi Activecat,
I still don't understand why you don't want the decimation filters -- you
*need* them, unless you want to have massive aliasing of signals >>200kHz
into your bandpass signal. Decimation without filtering is a big signal
theoretical no-go.
I think I effectively need you to explain in something like a frequency
chart, which information you want to get out of the USRP.
Greetings,
Marcus
What I try to get out of the USRP, is the raw data that is shown in
figure 2-8 of the attached file.
If this is just an intellectual exercise, you can just use a BASIC_RX
card, which has analog bandwidth up to 250MHz, and apply a 150Mhz signal
to it, tuning the N2xx to where the alias frequency should appear and
confirm that, yes, there really is a Nyquist sampling theorem.
I have successfully applied 4.00001GHz signal to a BASIC_RX card, with
sample rate of 200kHz it gains a 10kHz intermediate frequency. This is a
successful attempt.
When I want to publish the result, others may question me whether the
sampling is really done at 200kHz, or in fact 100MHz.
I am stumble.
_______________________________________________
_______________________________________________
USRP-users mailing list
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[Daniele Nicolodi]

Post by Activecat
In fact I am trying to perform bandpass sampling.

What is bandpass sampling? I never heard of it.

Post by Activecat
I need the host (PC) to get the raw sample at 200kS/s, ideally the
samples should not be "pre-processed" by CIC or any other FPGA logic.

There is no much difference between having an ADC sampling at 100 MHz
and then decimate it down to 200 kHz applying the correct filtering, and
having an ADC sampling directly at 200 kHz. The first solution it
actually better, because given the same ADC noise you gain a factor
sqrt(100e6 / 200e3) in noise floor.

Why do you need the "raw samples"?

Post by Activecat
As the 100MS/s of the ADC cannot be changed, it seems that I have no
other choice but to reprogram the FPGA..

Reprogram the FPGA to do what exactly? I don't understand what you are
trying to obtain.

Cheers,
Daniele

[Activecat]

On Tue, Aug 12, 2014 at 9:01 PM, Daniele Nicolodi via USRP-users <

Post by Daniele Nicolodi

Post by Activecat
In fact I am trying to perform bandpass sampling.

What is bandpass sampling? I never heard of it.

Bandpass sampling is also known as undersampling or subsampling.

Here is some basic:
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CCcQFjAB&url=http%3A%2F%2Fwww.utdallas.edu%2F~raja1%2FEE4361%2520Spring%252014%2FLecture%2520Notes%2FBandpass%2520Sampling.pdf&ei=ERzqU9bsEYa58gXFvIGIDw&usg=AFQjCNFgvN6HaSGoSWXzcGI4go93dTw17A&sig2=TK4RLz5fbY-1QnBWQ8BDAg&bvm=bv.72676100,d.dGc

Post by Daniele Nicolodi

Post by Activecat
I need the host (PC) to get the raw sample at 200kS/s, ideally the
samples should not be "pre-processed" by CIC or any other FPGA logic.

There is no much difference between having an ADC sampling at 100 MHz
and then decimate it down to 200 kHz applying the correct filtering, and
having an ADC sampling directly at 200 kHz. The first solution it
actually better, because given the same ADC noise you gain a factor
sqrt(100e6 / 200e3) in noise floor.
Why do you need the "raw samples"?

This involves theoretical research, that's why it is best to start with raw
samples.

Post by Daniele Nicolodi

Post by Activecat
As the 100MS/s of the ADC cannot be changed, it seems that I have no
other choice but to reprogram the FPGA..

Reprogram the FPGA to do what exactly? I don't understand what you are
trying to obtain.

Reprogram the FPGA so that it let all samples pass through transparently.

[Activecat]

Post by Daniele Nicolodi
What is bandpass sampling? I never heard of it.
Bandpass sampling is also known as undersampling or subsampling.
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CCcQFjAB&url=http%3A%2F%2Fwww.utdallas.edu%2F~raja1%2FEE4361%2520Spring%252014%2FLecture%2520Notes%2FBandpass%2520Sampling.pdf&ei=ERzqU9bsEYa58gXFvIGIDw&usg=AFQjCNFgvN6HaSGoSWXzcGI4go93dTw17A&sig2=TK4RLz5fbY-1QnBWQ8BDAg&bvm=bv.72676100,d.dGc

The link may not work, attached is the pdf file.

[Marcus Müller]

Hi Activecat,

Post by Activecat

Post by Daniele Nicolodi
Why do you need the "raw samples"?

This involves theoretical research, that's why it is best to start with raw
samples.

No, it's not, because it's impossible ;)

This is the whole point of this discussion: Theory.
By sampling theory (and in practice) you get aliases at (f-f_sample)*N.

Also, by the the same theory, these aliases look *exactly* the same as
when you shift by multiplying with a complex sine of the difference
frequency. The errors introduced in the FPGA doing this multiplication
are so small that for all theoretical (and practical) purposes they are
outweighed by other effects.

Since you *cannot* get the raw 100MSamples out of the device, you *must*
decimate.
Decimation introduces aliases (because it kind of is sampling), and in
non-undersampling scenarios you filter out everything above the
post-decimation bandwidth to avoid having them added to your bandpass
signal.
Now, with undersampling, you want to filter out everything but a
bandpass region that you want aliased into the baseband. Now, that
bandpass filter can be seen as nothing but a frequency shifted lowpass,
i.e. a low pass filter that has been multiplied with a complex sine;
which again is equivalent mathematically to frequency shifting the
signal, and then lowpas filtering it. And that's *exactly* what the USRP
does.

Greetings,
Marcus

[Daniele Nicolodi]

Post by Activecat
On Tue, Aug 12, 2014 at 9:01 PM, Daniele Nicolodi via USRP-users

Post by Activecat
In fact I am trying to perform bandpass sampling.

What is bandpass sampling? I never heard of it.
Bandpass sampling is also known as undersampling or subsampling.

It's the first time I see this technique addressed with this name.

Post by Activecat
Reprogram the FPGA so that it let all samples pass through transparently.

What do you want to do with the 100 MS/s then? You cannot stream all of
them through the network interface!

Cheers,
Daniele

[Activecat]

Post by Daniele Nicolodi

Post by Activecat
On Tue, Aug 12, 2014 at 9:01 PM, Daniele Nicolodi via USRP-users

Post by Activecat
In fact I am trying to perform bandpass sampling.

What is bandpass sampling? I never heard of it.
Bandpass sampling is also known as undersampling or subsampling.

It's the first time I see this technique addressed with this name.

Post by Activecat
Reprogram the FPGA so that it let all samples pass through transparently.

What do you want to do with the 100 MS/s then? You cannot stream all of
them through the network interface!

Ideally I want to "turn-off" the CIC function, and I wish the ADC to sample
at 200kHz, and send all "raw data" to the host (PC).

Since the N210 ADC is running at 100MHz and this cannot be changed, the
workaround is to get samples from USRP at 100MS/s and discard 499 out of
every 500 samples.

Note: 100MHz / 200kHz = 500

[Daniele Nicolodi]

Post by Activecat
Ideally I want to "turn-off" the CIC function, and I wish the ADC to
sample at 200kHz, and send all "raw data" to the host (PC).
Since the N210 ADC is running at 100MHz and this cannot be changed, the
workaround is to get samples from USRP at 100MS/s and discard 499 out of
every 500 samples.

If your application requires such modifications to the N210 USRP I would
question whether it is the right hardware for the job. I believe a much
simpler ADC card would be better suited for what you want to do.

Cheers,
Daniele